In semiconductor manufacturing, chemical mechanical polishing (CMP) is a process designed to polish a substrate and to provide a global planarized surface. The CMP process can be implemented at various integrated circuit (IC) fabrication stages, such as a shallow trench isolation (STI) process and a dual damascene process. A CMP process should be stopped at a proper time (referred to as endpoint) such that there is no over polishing or under polishing. During a CMP process, a pad is used and will gradually wear out. CMP behavior will change along with the pad's condition. Existing CMP systems do not consider the pad condition and can not precisely determine the endpoint accounting for the pad condition. For example, a CMP system Mirra developed by Applied Materials uses a fixed algorithm to determine the endpoint regardless the pad condition. Thus, over polishing, under polishing, or unacceptable dishing or erosion may arise during the CMP process, introducing shorting, opening, or performance or reliability issues. Therefore, to address the above issues, there is a need for a CMP system and method that precisely determines the CMP endpoint by considering the pad condition.